Presently, the top contact process window is small and normally insufficient for inserting emerging memories, e.g., MRAM, resistive random-access memory (ReRAM) and ferroelectric random-access memory (FeRAM), into back-end-of-line (BEOL) low-K process steps because the critical dimension (CD) of these memory cells are smaller compared to normal BEOL process variations from planarization, e.g., the top connection of an MRAM has no margin because the CD of a magnetic tunnel junction (MTJ) is small and variations from planarization are much larger. In addition, the conventional spin-on-glass (SOG) and etch back processes result in higher SOG dielectric constant than the BEOL low-k that defeats the resistance capacitance (RC) benefit of BEOL low-k. Further, these processes neither cater to localized array topography nor to process variations.
Referring to FIG. 1 (cross-sectional view), the top connection for a known MRAM 101 and pillar contact 103 has no margin because of smaller CD and larger variations from planarization. The deposition of low-K layer 105, e.g., formed of hydrogenated oxidized silicon carbon (SiCOH), over the MRAM 101 and pillar contact 103 results in varying heights and the chemical mechanical planarization (CMP) time to planarize the topography results in bad uniformity. In addition, the taller pillar contact 103 may cause an uneven height that a CMP may not uniformly planarize, adding to the cost and complexity of the process. Further, if there is a contact etch process, the trapezoids 107 illustrate how the contact bottom varies due to the SiCOH 105 typography.
A need therefore exists for a methodology for forming a uniform low-k topography over a memory array with a large process window at a low cost.